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Micron Targets 2027 for NAND Chips That Double Storage Density

The new G11 generation will use wafer bonding to reach 42 Gb/mm2 and boost I/O speeds by 50%.

By Chloe Kapoor ·

Illustration for: Micron Targets 2027 for NAND Chips That Double Storage Density
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Micron Technology plans to begin mass production of its G11 3D NAND flash chips in the second half of 2027. The company stated this week that the new memory will provide approximately twice the storage density of its current G9 generation. This upgrade aims to increase capacity while reducing the power required for data transfer.

The shift from the current G9 technology to the G11 platform marks a jump in density from roughly 21 Gb/mm2 to 42 Gb/mm2 in triple-level-cell form. Micron projects that input/output speeds will rise by up to 50%, moving from 3,600 MT/s to 5,400 MT/s. The company also expects the energy cost for transferring each bit to drop by more than 25% compared to existing designs.

A core engineering change in G11 involves wafer-on-wafer bonding. This method allows Micron to fabricate the NAND array and the peripheral circuitry on separate wafers. Each wafer is processed using a technique optimized for its specific function before the two are bonded together. Scott DeBoer, Micron’s president and chief technology and products officer, described this approach as the appropriate timing for introducing the technology.

DeBoer referred to G11 as the world’s most advanced NAND. He confirmed that the design relies on wafer-on-wafer bonding, a technique already employed by Chinese competitor YMTC. Micron has previously used CMOS-under-array designs, but bonding provides greater flexibility to optimize memory arrays and logic components independently. The new chips are intended for high-capacity solid-state drives in client devices and data centers, as well as storage solutions for artificial intelligence workloads.

The G11 design will exceed 400 layers, although Micron has not disclosed the exact number of active wordlines. The company stated that the design features an industry-leading memory cell pitch. This suggests that the density increase results from both additional layers and smaller cell dimensions. Micron plans to share further technical specifications in 2027, closer to the start of high-volume production.

Beyond G11, Micron intends to continue scaling in three dimensions. The company is developing high-mobility materials and ultra-dense cell architectures to improve transistor characteristics and reduce energy consumption. DeBoer noted that the roadmap focuses on new materials and densifying cell architecture. He added that the industry generally scales by adding layers and shrinking cell dimensions, a trend expected to continue as demand for NAND storage remains strong.

Source: Tom's Hardware

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